The present application relates generally to analog-to-digital converters, and more specifically to systems and methods of dynamically compensating for zero level offset errors introduced into output signals generated by analog-to-digital converters. The presently disclosed system and method of dynamic offset compensation is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated digital signal processor devices.
It is well known that output signals generated by Analog-to-Digital Converters (ADCs) frequently include unwanted DC voltage components that cause zero level offsets to be present in the signals. For example, an ADC output signal may have a positive zero level offset or a negative zero level offset. Such zero level offsets are often sources of error, especially when the output signal level is low. In general, the zero level offset error of an analog-to-digital converter is defined as the non-zero digital conversion of a 0 volt analog input signal. Ideally, the digital conversion of a 0 volt analog signal is a 0 volt digital signal.
Conventional analog-to-digital converters typically include a high reference voltage pin (e.g., REF+) and a low reference voltage pin (e.g., REF−) having respective high and low reference voltages (e.g., Vref+ and Vref−) applied thereto. Analog input voltage levels greater than Vref+ are normally converted by an ADC to a digital signal represented by all ones (e.g., 11111111), and analog input voltage levels less than Vref− are normally converted by an ADC to a 0 volt digital signal represented by all zeros (e.g., 00000000). In this case, it is assumed that the analog-to-digital converter is an 8-bit ADC. To determine the zero level offset error for such an ADC, an analog voltage level (DC) is typically applied to the REF− pin corresponding to the level that should be converted by the ADC to 0 volts. Next, this same voltage level is applied to the input of the ADC, and the positive zero level offset error is determined by taking the difference between the actual non-zero ADC output and the expected 0 volt ADC output. In the event the ADC has a negative zero level offset error, the highest input analog voltage level is determined that causes the ADC to generate a 0 volt digital output. This voltage level is then converted into equivalent bits to determine the negative offset error.
One way of compensating for zero level offset errors in analog-to-digital converters is to apply a fixed non-zero analog voltage level to the low reference voltage pin, REF−. For example, a suitable fixed voltage level may be applied to the REF− pin to compensate for a pre-defined worst-case offset error. However, this compensation technique has drawbacks in that it does not reduce the range of the ADC offset error, but merely shifts the range of the offset error. For example, an ADC may exhibit an offset error of ±80 LSB (offset error range of 160 LSB). In the event a voltage level corresponding to 80 LSB were applied to the low reference voltage pin of the ADC, the range of the ADC offset error would typically shift from ±80 LSB to 0–160 LSB without reducing the offset error range. In addition, this compensation technique fails to take into account; potential long-term changes in offset currents and voltages, which can cause variations in the range of the offset error.
Another known technique to compensate for zero level offset errors in ADCs is to apply a dynamically controlled analog voltage level to the low reference voltage pin, REF−. For example, a conventional dynamic zero level offset compensating system may include programmable Digital Signal Processor (DSP) circuitry coupled to a Digital-to-Analog Converter (DAC) for generating an analog voltage level dynamically controlled by the DSP circuitry. Because the DSP circuitry is programmable, dynamic compensation for variations in the ADC circuitry may be performed via software during system operation. However, this technique of dynamically compensating for zero level offset errors also has drawbacks in that it can be very costly to implement.
Instead of using a dedicated digital signal processor to implement dynamic compensation of ADC offset errors, an integrated digital signal processor device including DSP circuitry and a multi-bit ADC may be employed. For example, the TMS320F2812 Digital Signal Processor manufactured by Texas Instruments® Inc., Dallas, Tex., USA, includes DSP circuitry and a 12-bit ADC module. To dynamically compensate for zero level offset errors in the 12-bit ADC of the TMS320F2812 device, an external DAC device may be employed to convert a digital control voltage generated by the DSP circuitry into a corresponding controlled analog voltage, which may then be applied to the low reference voltage input of the integral 12-bit ADC. However, this technique of dynamically compensating for ADC offset errors can also be costly to implement.
It would therefore be desirable to have a system and method of dynamically compensating for ADC offset errors that avoids the drawbacks of the above-described conventional techniques.